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28C04A
4K (512 x 8) CMOS EEPROM
FEATURES
* Fast Read Access Time--150 ns * CMOS Technology for Low Power Dissipation - 30 mA Active - 100 A Standby * Fast Byte Write Time--200 s or 1 ms * Data Retention >200 years * Endurance - Minimum 104 Erase/Write Cycles - Automatic Write Operation - Internal Control Timer - Auto-Clear Before Write Operation - On-Chip Address and Data Latches * Data Polling * Chip Clear Operation * Enhanced Data Protection - VCC Detector - Pulse Filter - Write Inhibit * 5-Volt-Only Operation * Organized 512x8 JEDEC standard pinout - 24-pin Dual-In-Line Package - 32-pin PLCC Package * Available for Extended Temperature Ranges: - Commercial: 0C to +70C - Industrial: -40C to +85C
PACKAGE TYPES
DIP
A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS
*1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
Vcc A8 NC WE OE NC CE I/O7 I/O6 I/O5 I/O4 I/O3
32 Vcc 31 WE 18 19
28C04A
2 NC 1 NU
4 A7 3 NC
PLCC
A6 A5 A4 A3 A2 A1 A0 NC I/O0
5 6 7 8 9 10 11 12 13
30 NC 29 A8 28 NC 27 NC 26 NC 25 OE 24 NC 23 CE 22 I/O7 21 I/O6 20
28C04A
14 15 16
* Pin 1 indicator on PLCC on top of package
BLOCK DIAGRAM
I/O0 I/O7
DESCRIPTION
The Microchip Technology Inc. 28C04A is a CMOS 4K non-volatile electrically Erasable and Programmable Read Only Memory (EEPROM). The 28C04A is accessed like a static RAM for the read or write cycles without the need of external components. During a "byte write", the address and data are latched internally, freeing the microprocessor address and data bus for other operations. Following the initiation of write cycle, the device will go to a busy state and automatically clear and write the latched data using an internal control timer. To determine when a write cycle is complete, the 28C04A uses Data polling. Data polling allows the user to read the location last written to when the write operation is complete. CMOS design and processing enables this part to be used in systems where reduced power consumption and reliability are required. A complete family of packages is offered to provide the utmost flexibility in applications.
VSS VCC CE
OE
WE
Data Protection Circuitry Chip Enable/ Output Enable Control Logic
I/O1 I/O2 Vss NU I/O3 I/O4 I/O5
17
Auto Erase/Write Timing
Data Poll
Input/Output Buffers
Program Voltage Generation
A0
L a t c h e s
A8
Y Decoder
Y Gating
X Decoder
4K bit Cell Matrix
(c) 1998 Microchip Technology Inc.
DS11126G-page 1
28C04A
1.0
1.1
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS*
TABLE 1-1:
Name A0 - A8 CE OE WE I/O0 - I/O7 VCC VSS NC NU
PIN FUNCTION TABLE
Function Address Inputs Chip Enable Output Enable Write Enable Data Inputs/Outputs +5V Power Supply Ground No Connect; No Internal Connection Not Used; No External Connection is Allowed
VCC and input voltages w.r.t. VSS........ -0.6V to + 6.25V Voltage on OE w.r.t. VSS ...................... -0.6V to +13.5V Output Voltage w.r.t. VSS..................-0.6V to VCC+0.6V Storage temperature .......................... -65C to +125C Ambient temp. with power applied........ -50C to +95C
*Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-2:
READ/WRITE OPERATION DC CHARACTERISTICS
VCC = +5V 10% Commercial (C): Tamb = Industrial (I): Tamb = 0C to +70C -40C to +85C Conditions
Parameter Input Voltages Input Leakage Input Capacitance Output Voltages Output Leakage Output Capacitance Power Supply Current, Active Power Supply Current, Standby
Status Logic `1' Logic `0'
Symbol VIH VIL ILI CIN
Min 2.0 -0.1 -10
Max VCC+1 0.8 10 10
Units V V A pF V V A pF mA mA mA A
VIN = -0.1V to VCC+1 VIN = 0V; Tamb = 25C; f = 1 MHz IOH = -400 A IOL = 2.1 mA VOUT = -0.1V TO VCC + 0.1V VIN = 0V; TAMB = 25C; f = 1 MHz f = 5 MHz (Note 1) VCC = 5.5V CE = VIH (0C to +70C) CE = VIH (-40C to +85C) CE = VCC-0.3 to VCC+1 OE = VCC All inputs equal VCC or VSS
Logic `1' Logic `0'
VOH VOL ILO COUT
2.4 0.45 -10 10 12 30 2 3 100
TTL input
ICC
ICC(S)TTL TTL input TTL input ICC(S)TTL CMOS input ICC(S)CMOS
Note 1: AC power supply current above 5 MHz; 1 mA/MHz.
DS11126G-page 2
(c) 1998 Microchip Technology Inc.
28C04A
TABLE 1-3: READ OPERATION AC CHARACTERISTICS
AC Testing Waveform: Output Load: Input Rise and Fall Times: Ambient Temperature: 28C04A-15 Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE to OE High Output Float Output Hold from Address, CE or OE, whichever occurs first Endurance Sym Min tACC tCE tOE tOFF tOH -- 0 0 1M -- Max 150 150 70 50 0 0 1M -- Min Max 200 200 80 55 0 0 1M -- Min Max 250 250 100 70 ns ns ns ns ns cycles 25C, Vcc = 5.0V, Block Mode (Note) OE = CE = VIL OE = VIL CE = VIL VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL = 0.8V 1 TTL Load + 100 pF 20 ns Commercial (C): Tamb = 0C to +70C Industrial (I): Tamb = -40C to +85C 28C04A-20 28C04A-25 Units Conditions
Note: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-1:
VIH Address VIL VIH CE VIL
READ WAVEFORMS
Address Valid
tCE(2)
VIH OE VIL VOH Data VOL WE VIH VIL Notes: (1) tOFF is specified for OE or CE, whichever occurs first (2) OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE (3) This parameter is sampled and is not 100% tested tACC tOE(2) High Z tOFF(1,3) tOH Valid Output High Z
(c) 1998 Microchip Technology Inc.
DS11126G-page 3
28C04A
TABLE 1-4: BYTE WRITE AC CHARACTERISTICS
AC Testing Waveform: Output Load: Input Rise/Fall Times: Ambient Temperature: Parameter Address Set-Up Time Address Hold Time Data Set-Up Time Data Hold Time Write Pulse Width Write Pulse High Time OE Hold Time OE Set-Up Time Data Valid Time Write Cycle Time (28C04A) Write Cycle Time (28C04AF) Symbol tAS tAH tDS tDH tWPL tWPH tOEH tOES tDV tWC tWC Min 10 50 50 10 100 50 10 10 1000 1 200 VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL = 0.8V 1 TTL Load + 100 pF 20 nsec Commercial (C): Tamb= 0C to 70C Industrial (I): Tamb= -40C to 85C Max Units ns ns ns ns ns ns ns ns ns ms s Note 2 0.5 ms typical 100 s typical Note 1 Remarks
Note 1: A write cycle can be initiated be CE or WE going low, whichever occurs last. The data is latched on the positive edge of CE or WE, whichever occurs first. 2: Data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least until tDH after the positive edge of WE or CE, whichever occurs first.
FIGURE 1-2:
PROGRAMMING WAVEFORMS
VIH Address VIL VIH CE, WE VIL tDV Data In VIH VIL tOES VIH OE VIL tOEH tDS tAS tAH tWPL tDH
DS11126G-page 4
(c) 1998 Microchip Technology Inc.
28C04A
FIGURE 1-3: DATA POLLING WAVEFORMS
VIH
Address VIL Address Valid t ACC t CE t WPH
Last Written Address Valid
VIH
CE VIL
VIH
WE VIL
t WPL t OE
VIH
OE VIL
t DV VIH
Data VIL Data In Valid t WC I/O7 Out True Data Out
FIGURE 1-4:
CHIP CLEAR WAVEFORMS
VIH CE VIL VH OE VIH VIH WE VIL tW = 10ms tS = tH = 1s VH = 12.0V 0.5V tS tW tH
(c) 1998 Microchip Technology Inc.
DS11126G-page 5
28C04A
2.0 DEVICE OPERATION
2.4 Write Mode
The Microchip Technology Inc. 28C04A has four basic modes of operation--read, standby, write inhibit, and byte write--as outlined in the following table. Operation Mode Read Standby Write Inhibit Write Inhibit Write Inhibit Byte Write Byte Clear X = Any TTL level. CE L H H X X L IE L X X L X H WE H X X X H L I/O DOUT High Z High Z High Z High Z DIN The 28C04A has a write cycle similar to that of a Static RAM. The write cycle is completely self-timed and initiated by a low going pulse on the WE pin. On the falling edge of WE, the address information is latched. On rising edge, the data and the control pins (CE and OE) are latched.
2.5
Data Polling
Automatic Before Each "Write"
The 28C04A features Data polling to signal the completion of a byte write cycle. During a write cycle, an attempted read of the last byte written results in the data complement of I/O7 (I/O0 to I/O6 are indeterminable). After completion of the write cycle, true data is available. Data polling allows a simple read/compare operation to determine the status of the chip eliminating the need for external hardware.
2.6
Chip Clear
2.1
Read Mode
The 28C04A has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and is used to gate data to the output pins independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the output tOE after the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tACC-tOE.
All data may be cleared to 1's in a chip clear cycle by raising OE to 12 volts and bringing the WE and CE low. This procedure clears all data.
2.2
Standby Mode
The 28C04A is placed in the standby mode by applying a high signal to the CE input. When in the standby mode, the outputs are in a high impedance state, independent of the OE input.
2.3
Data Protection
In order to ensure data integrity, especially during critical power-up and power-down transitions, the following enhanced data protection circuits are incorporated: First, an internal VCC detect (3.3 volts typical) will inhibit the initiation of non-volatile programming operation when VCC is less than the VCC detect circuit trip. Second, there is a WE filtering circuit that prevents WE pulses of less than 10 ns duration from initiating a write cycle. Third, holding WE or CE high or OE low, inhibits a write cycle during power-on and power-off (VCC).
DS11126G-page 6
(c) 1998 Microchip Technology Inc.
28C04A
28C04A Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices.
28C04A F T - 15 I
/P Package: Temperature Range: Access Time: L = Plastic Leaded Chip Carrier (PLCC) P = Plastic DIP (600mill) Blank = 0C to +70C I = -40C to +85C 15 20 25 Blank T 150 ns 200 ns 250 ns Tube Tape and Reel "L" only
Shipping: Option: Device:
Blank = twc = 1ms F = twc = 200 s
28C04A
512 x 8 CMOS EEPROM
(c) 1998 Microchip Technology Inc.
DS11126G-page 7
M
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602-786-7200 Fax: 602-786-7277 Technical Support: 602 786-7627 Web: http://www.microchip.com
AMERICAS (continued)
Toronto
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ASIA/PACIFIC (continued)
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ASIA/PACIFIC
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EUROPE
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Italy
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Microchip Technology Inc. 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 516-273-5305 Fax: 516-273-5335
San Jose
Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955
Microchip received ISO 9001 Quality System certification for its worldwide headquarters, design, and wafer fabrication facilities in January, 1997. Our field-programmable PICmicroTM 8-bit MCUs, Serial EEPROMs, related specialty memory products and development systems conform to the stringent quality standards of the International Standard Organization (ISO).
All rights reserved. (c) 1998, Microchip Technology Incorporated, USA. 10/98
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS11126G-page 9
(c) 1998 Microchip Technology Inc.

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